Fails - Exact or Censored

Failure times are either EXACT or CENSORED

Right censored or suspended = Unit has survived when test is stopped

Interval censored = Unit has failed between "Last Inspection" and now

Left censored = Similar to Interval Censoring but "Last Inspection"/Start is 0

Extrapolating Accelerated Test TTF to Predict Use Level Lifetime

Collect TTF at multiple accelerated stress levels.
Fit TTF data to life-distribution (for eg. 2P Weibull) for each stress level, and estimate parameters - each distribution with different eta but same beta (for the same failure mechanism).

Life distribution characteristic (eta) is a function of stress & is equated to stress level using a given Life-Stress-Relationship (LSR) - for eg Eyering Model
Estimate model constants

Now, knowing model constants, estimate eta at various stress levels, including at use level. And knowing beta (for the given failure mechanism) use-level life distribution can be predicted.

FIT Rates

h(t) = hazard rate = f(t)/R(t)
Hazard rate is instantaneous failure rate. But usually, average failure rate for a given time period is more useful, for eg. failure rate per hour.

FIT rate is defined as ppm failure per 1000 hours or number of fails per 10^9 device hours.

Multiply hourly fail-rate by 10^9 to generate FIT rate.

Hourly fail rate = No of rejects / (No of devices x No of hours x AF)

FIT rate = Hourly fail rate x 10^9

No of rejects is determined by Chi-square distribution = [(x^2)/2], commonly at 60% confidence (alpha) and dof: 2r + 2

ASIC Types: CPU v/s FPGA

CPU is general purpose processor. Good for performing a wide variety of tasks but performance may not be optimal for any specific task or function.

FPGA is application & task specific, and is reprogrammable logic that can be reconfigured at customer's end to provide optimized performance for a specific function.

For instance, FPGA's may be used as accelerators or co-processors in HPC environments.

PoP Evolution

WB-PoP->FC-PoP->InFO: BDP->MLP->MEP->EDP

CSP - Package Formats

BD-CUF, OM-CUF, OM-CUF-ED, OM-MUF, OM-MUF-ED

Mold Embedded Packages (MEP)

Molded Embedded Packages seek to overcome warpage concerns and limitations in z-height that conventional PoP type packages suffer from, where hybrid wirebonded/stacked die memories are stacked on FCBGA logic/ASIC SoC's, as commonly found in AP's of high-end flagship smartphones.

For MEP, first the active logic device is flip-chip attached on a base substrate. Then Cu Core balls are used to mount the top substrate on the base substrate with the interstitial space between the 2 substrates being encapsulated by a molding resin. Finally, BGA solder balls are mounted on the bottom substrate.

Since MEP does not require any gap between top and bottom packages as required in a conventional PoP (BD or MLP-ED/OM), by nature of the package construction, it allows for thinner PoP form factors. Landing pads routed to the top-side of the MEP allow DDR/DRAM memory to be mounted in a PoP format without any limitations from the layout of the (embedded) logic die (unlike conventional PoP's), enabling wide I/O memory interconnect with high bandwidth. This also allows using thinner memories reducing package z-height. Further, MEP packages have good warpage characteristics owing to similar material /structures between top & bottom substrates.

TSV MEOL Process

Backside processing done at the OSAT on TSV wafers that involves TSV reveal & RDL/C4 interconnect processing, used in 2.5D/3D TSV package integration is commonly termed as MEOL. This involves wafer support system (WSS) for thin wafer handling/management (bonding/debonding), wafer thinning (Si-etch), TSV reveal & CMP, passivation (CVD), backside RDL, & back/front side bumping.

Larger body sizes implemented as FCxGA 2.5D TSV, while smaller body sizes are targeted for FCCSP 3D TSV.

System in Package

SiP implementation formats = MCM, POP, PiP, SxS, stacked die, 3D/2.5D TSV.
Combines multiple IC's with different functionalities into a single system or sub-system

Allows heterogeneous package integration. May contain surface mount discrete passives, integrated passive devices (IPD), used for analog/RF/mixed signal applications,can mix Si/SiGe/GaAs technolgies

Markets include RF/wireless (amplifiers, antenna, filters, oscillators, switch, GPS, BT), memory (SSD NAND/DDR), automotive (ECU, infotainment & telematics, sensory modules), IoT (microcontrollers, MEMS, power management, sensors & connectivity, mixed signal devices), power modules (PMIC, battery management).

Benefits include improved performance & functionalities at smaller footprint through heterogenous package integration with a modular approach allowing greater flexibility in supply chain & system design/integration during product development - and without the complexities/long cycle times/higher risk of SoC development. This allows faster time to market and reduces total cost of ownership.

FO-WLP: Chip-First v/s Chip-Last

Performance & functionality drive high I/O, fine pitch, high density interconnect requirements that require advanced package integration technologies. 3D/2.5D TSV based technologies enable such package integration, but these are burdened with high cost and process complexities. The other approach is "fan-out" or FO-WLP.

Some of the implementations of FO-WLP are eWLB (Infineon), RCP (Freescale), SWIFT (Amkor) & InFo (TSMC).

Traditionally, FO-WLP have used "chip-first" approaches, where chip is processed before RDL. Process includes wafer dicing, reconstitution, molding, RDL/bump formation & singulation. Otherwise, a "chip-last" technique may also be used where chip is processed after RDL. Here, the process steps involve first creating the RDL on a carrier wafer, chip-attaching the top-die (CoW), molding & singulation. In either case, generating the RDL requires expensive fab/foundry (BEOL) class equipment that may not be readiy available at the OSAT - so this adds to assembly cost.

A fan-out alternative that allows the OSAT's to leverage existing flip-chip assembly technology & infrastructure is FO chip-last package (FOCLP) that entails dicing, flip-chip assembly on 1L/coreless/ETS substrate in strip form, followed by molding & singulation. This does not require fab-class equipment for RDL processing, and therefore can keep costs low.

InFO - A new approach

Traditionally, high end smartphone chips have used PoP approach, where a wirebonded memory/LPDDR (DRAM) package is stacked on top of an AP that uses flip-chips interconnecting the SoC with a laminate substrate. InFO is a new packaging approach and an alternative to this traditional technique, disrupting the status quo, with numerous benefits in terms of improved performance & thinner package form factors.

InFO combines POP with FO-WLP packaging technologies, and stacks the wirebonded memory package on a FO-WLP SoC, that no longer requires flip-chip interconnects & the laminate substrate. This reduces the thickness of the package and improves performance by reducing the vertical path for signal propagation and allowing finer L&S routing capabilities by using an RDL instead of a laminate substrate. This in turn, improves SI/PI parasitics (crosstalk, impedance, transmission loss, PDN noise, jitter & leakage), improves DRAM/memory bandwidth and reduces power consumption. Package thermals on an InFO POP is expected to be superior to the conventional FCPOP's, with InFO generating lower Tjmax & Rja (for both logic SoC & DRAM) and being able to support larger TDP's for the same Tj. In addition, InFO provides high flexibility/capability for homogenous or heteregenous multi-chip package integration between active and/or passive devices, either at 2D using RDL or 3D with TIV (Through InFO Vias).

Advanced Package Integration Implementation

Infineon: eWLB, Freescale: RCP (Redistributed Chip Package) -> First examples of WLFO implementation
STMicroelectronics uses 3D-eWLB
ASE has FOPOP technology
Amkor POSSUM is implementation of Altera's ASIC + FPGA integration

Apple A8/A9 processor is 3D-POP using conventional FC/WB techniques integrating AP and Elpida memory (DDR3/4). Memory is wirebond BGA package stacked on AP that uses FC technology on a laminate substrate
Apple A10 (used in iPhone7) instead uses InFO package technology that combines the LPDDR/memory wirebond BGA package with a FO-WLP that eliminates the need for FC interconnects and replaces the laminate substrate with a RDL, thinning form factor and improving performance by reducing signal path and SI/PI parasitics.

Samsung has DDR4 DRAM modules that stacks multiple chips with 3D TSV integration
Micron has HMC DRAM memory stack that integrates 3D DRAM/DDR memory stack with logic controller with TSV providing high bandwidth memory, implemented in Altera STRATIX and Intel Knight's Landing platforms
AMD Fury Graphics uses Hynix HBM integrated with the ASIC/SoC with 2.5D TSV interconnect based approach.

2.5D TSV MEOL flows

CoC/CoW CHIP-LAST

Interposer (TSV/BEOL/front side pads) from fab -> Front-side carrier bond (to handle thin interposers) -> TSV reveal / Si etch, TSV remove (CVD/CMP), backside RDL + C4 -> Flip & rebond carrier on backside -> CoW top die attach -> Carrier debond & dicing -> Module attach to substrate

This is good for large die & thin core substrates.

CoS

Interposer (TSV/BEOL/front side pads) from fab -> Front-side carrier bond (to handle thin interposers) -> TSV reveal / Si etch, TSV remove (CVD/CMP), backside RDL + C4 -> Carrier debond & dicing -> Interposer to substrate attach -> Top die attach to module

Leverage FCBGA process, low cost.

TSV-free approach / SLIM (Amkor) (CoS)

TSV-free Interposer (NO TSV/BEOL/front side pads) from fab -> Front-side carrier bond (to handle thin interposers) -> Si etch , backside RDL + C4 -> Carrier debond & dicing -> Interposer to substrate attach -> Top die attach to module

2.1D / Package Organic Interposer

Typical layer count could be 3+1+2+2: 3 layers with 2/2 L&S, 1 BU (above core) + 2 Core + 2 BU (below core)

WLCSP & New Integration Technologies

FO-WLP -> InFO PoP (TSMC) and SWIFT (Amkor)

Traditional FO-WLP (or WLFO) use "chip-first" approaches. This needs committing expensive KGD before the wafer reconstitution/reconfiguration process and is therefore at risk of yield loss from the RDL build up process. Also, capabilities of photoresist/dielectric processing with steppers/masks are challenged by the planarity of the wafer-level molding process, resulting in limitations in the design rules for these packages, with the tightest L&S being in the range of 6-10um. Typically only 1 or 2 RDL layers can be supported. Additionally, 3D POP package formats have new complexities, since those entail complex laser drilling/Cu plating for the TMV's/Cu Pillars on back side of the molded wafers to establish the 3D interconnects to the front side RDL.

In contrast, SWIFT uses a "chip-last" approach, since the RDL/backside is first separately built up on a carrier wafer, and then the KGD is chip-attached using a CoW approach. Since RDL buildup is now done pre-molding, the dielectric topology/planarity allows much finer L&S with stepper/mask capabilities, allowing upto 2/2 L&S and upto 3 RDL layers. This technology is also compatible with large die / package body sizes, supports upto 30um die pitch (Cu ubumps) and allows for 3D PoP integration through TMV's or Cu posts/pillars.

SLIM/SWIFT are package integration technologies developed by Amkor to bridge the L/S routing capability gap between applications needing TSV (<2um L&S) v/s standard packaging (>5um), primarily targeted for WLP - but also extended to flip-chip packages, leveraging conventional techniques & capabilities, allowing for high density & smaller footprints at relatively low cost. SLIM uses TSV-free interposer wafers (but retains BEoL & RDL, allowing <2um L&S routing) that simplifies interposer MEOL process (by eliminating need for CVD/CMP for TSV reveal during interposer MEOL), thins package form factor and reduces cost & simplifies supply chain (by allowing use of TSV-free wafers). SWIFT, on the other hand, uses passive carrier / interposer wafers that do not contain TSV or BEOL (but retains RDL, allowing 2-5um L&S). Top die could be attached on using CoW approach for both SLIM/SWIFT followed by wafer molding, interposer MEOL and topside RDL routing for POP as needed.

A guideline for NPI milestones

System in Package

SiP = ASIC SoC (CMOS Logic) + HBM (DRAM stack) on
-2.5D Si interposer w/ TSV (CoS or CoW assembly flow) (L&S: <2um, highest cost)
-2.5D Si interposer w/o TSV (or SLIM) (CoS or CoW assembly flow) (L&S: <2um, medium cost)
-2.1D organic interposer or POI or iTHOP (L&S: 2-10 um, medium to possibly lower cost)

Packaging Technology

1st level interconnects: FC or WB

Flip Chip Attach:
MR (SnAg or CuP w/ SOP or CuBOL w/o SOP) w/CUF or MUF
TCFC (TCNCP or TCNCF or TCCUF)

Substrate:
Singulated or strip
ETS or SAP

Package:
BGA, LGA, CSP, POP, QFN, WLP, SiP

System Cooling v/s TDP

System Cooling = Rca & Tambient

As system cooling improves (reducing Rca & Tambient), solution can support larger TDP's.

For any given system cooling, Indium can support larger TDP compared to Poly TIM
For any given TDP, more system cooling (or lower Rca / lower Tamb) is needed for poly TIM solution v/s Indium TIM.

As power increases, case temperature has to be progressively lowered through system cooling, to maintain the same junction temperature. When the power increases, and the case temperature is not controlled (effectively by the system cooling), then junction temperature will rise.

When junction temperature exceeds a certain pre-set threshold (usually Tjmax), DVFS will trigger, reducing voltage and frequency, in turn reducing power (and computing performance), and thereby bringing the junction temperature down.

Datacenter Anatomy

CPU +components => NODES => BLADES/SLEDS + CHASSIS => RACKS => CLUSTERS