Wafer Level Chip Scale Packaging (WLCSP)
www.3dic.org/WLCSP
Wafer Level Chip Scale Packaging (WLCSP) is a microelectronic packaging technology, with which the manufacturing process steps are performed at the wafer level rather than on individual chips to achieve a package that is essentially the same size as the die. It evolves from the Flip-Chip packaging, eliminating the substrate. The basic structure of the WLCSP has an active chip surface with polymer coatings and bumps (BGA) with bare silicon exposed on the remaining sides and back of the die. The die can also be encapsulated to improve mechanical robustness and resistance to chipping, cracking and handling damage, and reliability. Comparing to fan-out wafer level package (FOWLP), it can be also termed as fan-in wafer level package (FIWLP).
Fan-Out Wafer-Level Packaging (FOWLP)
www.3dic.org/FOWLP
Fan-out wafer-level packaging (FOWLP) is a is an enhancement of standard wafer-level packaging (WLP, also known as WLCSP) for a greater number of external I/Os and system-in-package (SiP) solutions. FOWLP involves dicing chips on a silicon wafer, and then very precisely positioning the known-good chips on a thin “reconstituted” or carrier wafer/panel, which is then molded, following by making redistribution layer atop the molded area (chip and fan-out area), and then forming solder balls on top.
Advantages
"Fan-out is perhaps the biggest thing to hit the semiconductor industry since immersion lithography and high-k dielectrics."[5]
Fan-out Wafer Level Packages like eWLB offer the following differentiated advantages:
· Over Flip-Chip Packaging:
o Slightly smaller footprint (clearance distances to the edges are smaller)
o Thinner package
o Substrate-less package (shorter interconnections meaning higher electrical performance and cheaper in the long run)
o Future potential for SiP and 3D integration
o Lower thermal resistance
o Simplified supply chain infrastructure
· Over Fan-In WLCSP:
o Higher board-level reliability
o Fan-out area to counter the pad limitation issue, adaptable to customer needs
o Only confirmed known good dice are packaged
o Potential for SiP integration
o Lower thermal resistance
o Built-in back-side protection
o No restriction in bump pitch
Chip-first (mold-first) and Chip-last (RDL-first) FOWLP
Chip-first is a process whereby the die is attached to a temporary or permanent material structure prior to making the RDL that will extend from the die to BGA interface. In this manner, the yield loss associated with creating the RDL occurs after the die is mounted, subjecting the die to potential loss.
In chip-last prosess, RDL is created first and then the die is mounted. In this flow, the RDL structures can either be electrically tested or visually inspected for yield loss, thereby avoiding placing good die on bad sites.
For low I/O die, where RDL is minimal and yields are very high (>99%), a chip-first flow is preferred. However, for high value die (large I/O), a chip-last process is preferred.
FOCLP
www.3dic.org/FOCLP
Fan Out Chip Last Package (FOCLP) is a FOWLP technology developed by ASE. Copper pillar bumped die are mass reflowed onto a low cost coreless substrate, followed by overmolding, which also serves to underfill the die. The Cu pillars allow die connection at 50um or below, negating requirement for RDL on the die. The Cu pillars are bonded to one side of the copper trace (down to 15um L/S) and solder balls are directly bonded to the other side. This makes the “substrate” be effectively as thick as the copper in the traces and allows the final package to be as thin as 400um. Implementation with multiple die, inclusion of passives and 3D structures can all be implemented.
InFO
www.3dic.org/InFO
FO PoP (DRAM-on-Processor)
The Apple A10 SoC processor was packaged by using InFO PoP by TSMC. Above the processor InFO, there is a memory InFO packaging four Samsung LPDDR4 DRAM chips integrating 2 GB of DRAM in the iPhone 7, or 3 GB in the iPhone 7 Plus.
Apple A10 processor packaged by FO PoP.
SWIFT (Silicon Wafer Integrated Fan-out Technology)
www.3dic.org/SWIFT
SWIFT™ (Silicon Wafer Integrated Fan-out Technology) is a FOWLP technology developed by Amkor. On December 14, 2016, Amkor Technology Inc. (Nasdaq: AMKR) announced completion of product qualification for the SWIFT™.[1]
SWIFT Structure
SLIM (Silicon-Less Integrated Module)
www.3dic.org/SLIM
SLIM (Silicon-Less Integrated Module) is a packaging technology developed by Amkor. This SLIM™ chip packaging technology leverages the 2.5D sub-micron routing capability and no TSV is required, which lowers cost and improves electrical performance.
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