System in Package

SiP = ASIC SoC (CMOS Logic) + HBM (DRAM stack) on
-2.5D Si interposer w/ TSV (CoS or CoW assembly flow) (L&S: <2um, highest cost)
-2.5D Si interposer w/o TSV (or SLIM) (CoS or CoW assembly flow) (L&S: <2um, medium cost)
-2.1D organic interposer or POI or iTHOP (L&S: 2-10 um, medium to possibly lower cost)

Packaging Technology

1st level interconnects: FC or WB

Flip Chip Attach:
MR (SnAg or CuP w/ SOP or CuBOL w/o SOP) w/CUF or MUF
TCFC (TCNCP or TCNCF or TCCUF)

Substrate:
Singulated or strip
ETS or SAP

Package:
BGA, LGA, CSP, POP, QFN, WLP, SiP

System Cooling v/s TDP

System Cooling = Rca & Tambient

As system cooling improves (reducing Rca & Tambient), solution can support larger TDP's.

For any given system cooling, Indium can support larger TDP compared to Poly TIM
For any given TDP, more system cooling (or lower Rca / lower Tamb) is needed for poly TIM solution v/s Indium TIM.

As power increases, case temperature has to be progressively lowered through system cooling, to maintain the same junction temperature. When the power increases, and the case temperature is not controlled (effectively by the system cooling), then junction temperature will rise.

When junction temperature exceeds a certain pre-set threshold (usually Tjmax), DVFS will trigger, reducing voltage and frequency, in turn reducing power (and computing performance), and thereby bringing the junction temperature down.