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Tuesday, August 30, 2016

System in Package


SiP = ASIC SoC (CMOS Logic) + HBM (DRAM stack) on
-2.5D Si interposer w/ TSV (CoS or CoW assembly flow) (L&S: <2um, highest cost)
-2.5D Si interposer w/o TSV (or SLIM) (CoS or CoW assembly flow) (L&S: <2um, medium cost)
-2.1D organic interposer or POI or iTHOP (L&S: 2-10 um, medium to possibly lower cost)
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