3DIC.ORG [2.5D/3D]


Chip-on-Wafer-on-Substrate (CoWoS®)


www.3dic.org/CoWoS

TSMC CoWoS® (Chip-on-Wafer-on-Substrate) technology integrates multiple chips side-by-side onto a interposer containing through-silicon vias (TSVs) by chip-to-wafer bonding process, which is followed by CoW chip assembly onto a substrate (CoW-on-Substrate).

TSV Processes

Via-first TSV

Via-middle TSV

Via-last TSV before bonding

Via-last TSV after bonding



2.5D integration

www.3dic.org/2.5D integration

2.5D integration refers to the technology that stacks active chips side-by-side on a passive Si/glass interposer (or the intel's embedded multi-die interconnect bridge, EMIB), which enables high density chip-to-chip interconnects.

Xilinx Virtex-7 Interposer-based FPGAs

See main article 3D FPGA.
The Xilinx 2.5D FPGAs from the Virtex-7 family fabricated by TSMC using the CoWoS technology are the first commercially available silicon interposer-based FPGAs.

GPU and HBM DRAM on Si Interposer

The AMD Radeon R9 Fury X GPU released in June 2015 uses the 2.5 integration, in which HBM stacks and GPU are assembled on a Si interposer side-by-side. Another example is the Nvidia Tesla P100 GPU with HBM3D DRAM. It was officially announced in April 2016.

Embedded Multi-die Interconnect Bridge (EMIB)

See main article EMIB.
Embedded Multi-die Interconnect Bridge (EMIB) is an approach developed by Intel to in-package high density interconnect of heterogeneous chips. The EMIB contains no TSVs and is smaller comparing to interposer.

Altera FPGA with EMIB and HBM DRAM

See main article 3D FPGA.
Altera has launched the Stratix 10 FPGA which consists of HBM3D DRAM combined with FPGAs by using the EMIB.

Applications

Announcement DateCompanyProductHBM 1&2InterposerPackaging Technology
Oct 2013XilinxVirtex-7 2000T FPGAFPGA slicesSi TSV interposerCoWoS
June 2015AMDRadeon R9 Fury X GPU (Fiji)GPU + HBM1Si TSV interposerCoWoS
June 2015AlteraStratix 10 FPGAFPGA + HBM2EMIB (No TSVs)Multi-chips assembly on substrate with embeded EMIB
April 2016NvidiaTesla P100 GPUGPU + HBM2Si TSV interposerCoWoS

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