Bump Electromigration

Run kinetic study at multiple currents & temperatures to estimate Ea (activation energy) & n (current density exponent) in Black's equation:
MTTF = A J ^ (-n) exp [Ea/KT]
Resistance of the EM device is measured using 4-wire Kelvin structure, and an increase in R over a predefined threshold is considered to be a failure.
As a first step, the temperature sensor (that may be an on-die resistor or diode) is calibrated in the oven (set at a certain temp, for a low constant current) to generate R v/s temp (for the resistor) or V v/s temp (for the diode) to estimate TCR.
Then the oven is set to stress temperatures, and EM test structure is powered at stress current, to note initial change in R. Knowing TCR, delta R is equated to delta T. This is 'Joule Heating'.
Device temp = Oven Temp + DeltaT (Joule heating)
TTF data is collected and fit to an appropriate statistical distribution, which is then used to estimate MTTF from CDF plot (Cumulative % fails v/s time). Common distributions used to model EM data are Lognormal & Weibull.
Lognormal = sigma -> shape parameter, gives measure of distribution width.
Weibull = beta is shape parameter, eta is characteristic time (or time when 63.2% fails) MTTF obtained for multiple stress conditions (current & temp), based on distribution parameter estimation helps estimate Ea & n in Black's Equation. Once Ea & n have been estimated, lifetime/usage requirements (for eg 95C device temp & 5 years life) is used to predict Imax.

Local TIM Resistance Extraction

Run experiment on TTV at given P, Ta - and measure Tc (at lid center) and Tj at multiple die locations(local).
Setup thermal/FEA model and adjust heat transfer coefft until same Tc is obtained for given Ta and P.
Model will predict Tj (local) by estimating deltaT as P x Theta-jc from experiment (= [Tjlocal - Tc]/P)
Tj (local) = Tc + delta T
Force Tjlocal predicted from model to match Tjlocal from experiment, by adjusting local TIM1 thermal resistance.

Thick & thin lids : Impact on Thermal R

Theta-ja (local) = Theta jc (l) + Theta cs (l) + Theta sa (l)
From center to corner, Theta jc (l) increases, but due to 3D heat flow/ lateral heat spreading - theta cs (l) & theta sa (l) actually decrease. The resultant impact is that theta ja (l) also diminishes from center to corner.
This effect is more pronounced on thicker lids v/s thinner lids, since thicker lids allow more lateral heat spreading

Board components

SoC/Processor, logic chipsets (Southbridge), memory modules (DIMM, SODIMM, etc), PCI (network, storage)/AGP (graphic cards/GPU), SATA/IDE, power supplies & PMIC, heat sink, fans, wind tunnel / flow channel

MS&V

Vibration tests: JESD22-B103B

Swept sine tests: SHM with logarithmic sweep of frequency range from min-to-max, 4 times (4 mins each time) for each of X, Y, Z axes.
Peak acceleration (G), Peak displacement, crossover freq, freq range -for each use condition.
Example: Service condition 1, 20-2KHz, 4 mins/cycle, 4 cyc/axis, 3 axis.

Random vibration:Vibration applied for 30 minutes in each of the 3 orthogonal axes, X, Y, Z
RMS acceleration (G), RMS displacement, RMS velocity, - for each use condition
For each use condition, the selected test parameters above result in PSD values for different frequencies, generating plots/profiles showing PSD (intensity of acceleration power, measured in G^2/Hz) variation across a range of frequencies (2-500Hz).
Area under PSD-frequency plot is RMS acceleration (G)

Mechanical Shock JESD22-B110B:
Component or sub-assembly free-state: 5 shocks x 3 axes (X, Y, Z) x 2 directions/axis, minimum (total) 30 shocks
Sub-assembly mounted: 2 shocks x 3 axes (X, Y, Z) x 2 directions/axis, minimum (total) 12 shocks
Peak acceleration (G), pulse duration, velocity change, equivalent drop height.
Example: Service cond. B, 1500G, 0.5 ms, 5 times/axis, 6 axis

TCNCP process profile

Tpre-heat -> Tstage ->Initial high speed approach upto search height -> Approach at search speed -> Contact (min force)-> Force ramp to max force (pressurization), bond head temp increased from stage (standby) temp to Tcontact -> temp ramp to Tpeak or Tcure ->cooldown and head disengagement.
Tbond-head(standby) = T stage -> to minimize any risk of NCP entrapment
Tbond-head(standby) = T contact -> for best throughput
Tbond-head(standby) > T contact -> risk of NCP entrapment

TCNCP with OSP based surface finish

TCNCP requires OSP surface finish (low cost, fine pitch process margins v/s Sn based finishes, controlled solder wetting v/s EPIG finish). However this requires use of fluxing agents in NCP material, to remove oxides during thermal compression bonding. Also it is critical to remove any residual OSP from the pad, since the OSP can combine with by-products of the fluxing reaction and lead to NCP entrapment. This therefore, requires an OSP pre-clean step, which comprises of plasma-treatment & chemical deflux, ahead of TCB.

Power cycling

Motherboard, mux board & fan controller board - design & fabrication, DAQ system, Labview software, package + socket + heat sink + wind tunnel/flow channel, system integration, system setup & debug, calibration & testing.

PoP Evolution

PoP is popular package configuration for smartphones, since this format allows integration of AP/baseband logic with DDR(DRAM) in limited space constraints (footprint & height) while maximizing performance (high speed & bandwidth for memory). Over time, has evolved from WB-POP to FC-POP, and now from BD-PoP to MLP-PoP.

Increasing performance requirements drives larger logic die and package body size, thin core or coreless/ETS substrates, all of which increase warpage that make meeting tightening coplanarity requirements, very challenging. Package height constraints further necessitate thin die/substrates that increase coplanarity/warpage concerns.

In addition, higher memory performance drives need for fine pitch memory, that require smaller ball sizes, which translates to smaller collapsed height or clearance between top & bottom packages.

MLP-PoP is an approach that (1) alleaviates above concerns of warpage & coplanarity, by making use of an overmold that adds structural robustness to the package and (2) enables fine pitch memory by improving the clearance between the 2 packages, without needing excessive die thinning.

This may be MLP-ED (exposed die) or MLP-OM (overmold). ED reduces overall package thickness but slightly higher cop/warpage is the resulting tradeoff. Further, this may be MLP-CUF v/s MLP-MUF

However, MLP-PoP requires additional molding processes - and comes at a premium (cost). Lower cost alternative is to use BD PoP with CuBOL for the bottom package, that increases package to package clearance by reducing die-to-substrate standoff.

Apple A Series SoC

L-Gate methodology

L-Gate: Technology/Product Development
L-1: Explore / PC1
L 0: Define / PC2 & T/O
L 1: Enable/BKM determination
L 2: Implement/BKM optimization & corner
L 3: Qualify/BKM validate
L 4: Ramp/PRU
L 5: Production/HVM

TSV process

Front side:
Etch/Dielectric liner/barrier/seed/fill/RDL/passivation/landing pad

Back side:
Temp bond/backgrind & TSV reveal/MEOL/passivation/bump & debond

2.5D flows: CoW v/s CoS

2 primary flows: CoS and CoW (or CoC)
CoW/CoC may be chip-first (attach before interposer MEOL) or chip-last (after interposer MEOL)
Chip-first requires committing expensive die on interposer, without knowing interposer yield, but allows chip-attach on full thickness wafers. [Concern: Assemblly yield]
Chip-last uses KGD & finished interposer (or KGI) and therefore promises higher assembly yield, but requires thin interposer wafer handling (WSS) and therefore increases assembly cost. [Concern: Assembly cost]
CoS leverages existing flip-chip assembly infrastructure and allows test insertion before committing expensive BOM (logic/ASIC/memory die), but large interposer attach to substrate first, generates warpage concerns that may challenge ASIC/logic/memory die attach to interposer. [Concern: Assembly yield for large die]