Improved performance in modern-day microprocessors has been achieved through a combination of higher processor frequency / clock speeds, use of shrinking / advanced technology nodes & a generally increasing number of CPU cores in the SoC. Increasing core count translates to smaller physical size of the individual cores and a tightly packed core distribution/layout on the chip.
Smaller cores imply higher power density per core, which increases thermal resistance (Rja) of the packaging solution. Higher Rja at the same total power dissipation (P), increases the junction temperature (Tj). When Tj approaches a set/predefined threshold (commonly Tjmax), in modern day processors, DVFS (Dynamic Voltage Frequency Scaling) will trigger that reduces operating voltage and clock speed/frequency, which in turn, can directly impact computing performance. With reduced voltage & frequency, total power (P) and power density per core will both be lowered. When total power & core power density both scale downward by the same extent, since Rja (being defined by material & geometry parameters) remains relatively constant, this results in lowering of Tj. In this way, by means of DVFS, a correlation may be established between change in total power (P) and the impact on computing performance of the chip.
When cores are tightly packed around one another in the SoC floorplan, that can also adversely affect package thermals and Rja. It may be shown through simulation & analysis, that if power density per core is reasonably low and cores may be sufficiently spaced apart from each other in their distribution/layout on the SoC, the die power map may start approaching an idealistic uniform power density solution. This demonstrates that core distribution/layout and core spacing are an important items for consideration towards power map optimization during die floorplanning in early product design.
