Packaging Approaches
Speaking in broad terms, there are 2 overarching approaches to high density package integration
SoC:
- Large monolithic silicon
- High performance CPU/GPU/FPGA for compute, graphics, accelerators, servers, networking, servers, AI/ML neural networks in the cloud/edge
- Complex silicon w/ high transistor count/multi-layer backend stack for signal redistribution and long/complex fabrication cycles, higher cost, longer development cycles, can be justified for high end devices like processors (CPU, GPU)
- Combines multiple IC's with different functionalities into a single system or sub-system
- Multiple components packaged as one device (PoP, PiP, SxS, etc)
- IoT, RF/wireless, sensing modules, MEMS, automotive (ECU, infortainment, telematics)
- Simpler silicon design & fabrication process, lower cost, Flexibility in supply chain, shorter development cycles
Markets include RF/wireless (amplifiers, antenna, filters, oscillators, switch, GPS, BT), memory (SSD NAND/DDR), automotive (ECU, infotainment & telematics, sensory modules), IoT (microcontrollers, MEMS, power management, sensors & connectivity, mixed signal devices), power modules (PMIC, battery management).
Benefits include improved performance & functionalities at smaller footprint through heterogenous package integration with a modular approach allowing greater flexibility in supply chain & system design/integration during product development - and without the complexities/long cycle times/higher risk of SoC development. This allows faster time to market and reduces total cost of ownership.
Application & baseband processors for high end mobile devices can hybridize SoC and SiP integration approaches (ie.a SiP package can house an SoC as an individual component - for eg MEP or an advanced PoP, such as MLPoP, that packages an SoC logic die with memory).
High end / server-class SoC type devices are further borrowing SiP goals & objectives to pack multiple functionalities into a single system - by combining multiple SoC logic die and/or memories (DDR DRAM or HBM) in the same package - through high density integration technologies such as MCM, 3D TSV, silicon or organic interposer based methods (2.5D TSI, SLIM, POI etc)
SiP Package Integration w/ 2.5D
SiP = ASIC SoC (CMOS Logic) + HBM (DRAM stack) on
- 2.5D Si interposer w/ TSV (CoS or CoW assembly flow) (L&S: <2/2)
- 2.5D Si interposer w/o TSV (or SLIM) (CoS or CoW assembly flow) (L&S: 2/2)
- 2.1D organic interposer or POI or iTHOP (L&S: 2-10 um, medium to possibly lower cost)
2.5/3D SoC Adoption
- Image CMOS sensors/DSP, DRAM/flash memory stacks -> early adopters (Sony, SK Hynix, Micron, Samsung, Toshiba)
- High performance FPGA integration (Xilinx Vertex series)
- High performance graphics (AMD Fiji/Fury)
- Servers & networking (Altera, IBM, Huawei, Cisco)
CoW/CoC/CoS flows
2 primary flows: CoS and CoW (or CoC)
CoW/CoC may be chip-first (attach before interposer MEOL) or chip-last (after interposer MEOL)
Chip-first requires committing expensive die on interposer, without knowing interposer yield, but allows chip-attach on full thickness wafers. [Concern: Assemblly yield]
Chip-last uses KGD & finished interposer (or KGI) and therefore promises higher assembly yield, but requires thin interposer wafer handling (WSS) and therefore increases assembly cost. [Concern: Assembly cost]
CoS leverages existing flip-chip assembly infrastructure and allows test insertion before committing expensive BOM (logic/ASIC/memory die), but large interposer attach to substrate first, generates warpage concerns that may challenge ASIC/logic/memory die attach to interposer. [Concern: Assembly yield for large die]
TSV Fabrication Process
Front side:
Etch/Dielectric liner/barrier/seed/fill/RDL/passivation/landing pad
Back side:
Temp bond/backgrind & TSV reveal/MEOL/passivation/bump & debond
TSV / Interposer MEOL (Process)
Backside processing done at the OSAT on TSV wafers that involves TSV reveal & RDL/C4 interconnect processing, used in 2.5D/3D TSV package integration is commonly termed as MEOL. This involves wafer support system (WSS) for thin wafer handling/management (bonding/debonding), wafer thinning (Si-etch), TSV reveal & CMP, passivation (CVD), backside RDL, & back/front side bumping.
Larger body sizes implemented as FCxGA 2.5D TSV, while smaller body sizes are targeted for FCCSP 3D TSV.
Interposer MEOL Flows/Schemes
CoC/CoW CHIP-LAST
Interposer (TSV/BEOL/front side pads) from fab -> Front-side carrier bond (to handle thin interposers) -> TSV reveal / Si etch, TSV remove (CVD/CMP), backside RDL + C4 -> Flip & rebond carrier on backside -> CoW top die attach -> Carrier debond & dicing -> Module attach to substrate
This is good for large die & thin core substrates.
CoS
Interposer (TSV/BEOL/front side pads) from fab -> Front-side carrier bond (to handle thin interposers) -> TSV reveal / Si etch, TSV remove (CVD/CMP), backside RDL + C4 -> Carrier debond & dicing -> Interposer to substrate attach -> Top die attach to module
Leverage FCBGA process, low cost.
TSV-free approach / SLIM (Amkor) (CoS)
TSV-free Interposer (NO TSV/BEOL/front side pads) from fab -> Front-side carrier bond (to handle thin interposers) -> Si etch , backside RDL + C4 -> Carrier debond & dicing -> Interposer to substrate attach -> Top die attach to module
2.1D / Package Organic Interposer
Typical layer count could be 3+1+2+2: 3 layers with 2/2 L&S, 1 BU (above core) + 2 Core + 2 BU (below core)
Advanced Silicon/Package Integration Schemes at Intel
EMIB: Embedded Multi Interconnect Bridge
Localized high density package routing with ability to interconnect multiple die in an organic substrate without requiring TSV. Allows integration of multiple large die without being limited by reticle size of the interposer. Driven by the needs of high bandwidth CPU-DRAM (HBM) integration with low power consumption, and particularly attractive for large die. Leverages existing assembly processes and organic substrate technology. Lower cost than competing technologies of TSV & SLIM based package integration.
Thin silicon bridges are first fabricated using standard BEOL interconnects. An organic laminate substrate is also manufactured using standard processes upto the final build up layers. Here an additional process step is required wherein a cavity is created and the silicon bridge is inserted / and held in place with an adhesive before completing the final build up and localized fine microvia formation around the bridge region. During subsequent assembly, chip-attached is completed through a TCB/TCCUF process.
PoINT: Patch on Interposer
Implemented on Intel Skylake CPU, this uses a high density / thin core substrate (PATCH) stacked on lower density/ standard / lower cost organic laminate (INTERPOSER). Assembly involves first attaching SoC die to patch, and then attaching die+patch module to interposer. Due to concerns related to warpage of die+patch module, a low temp solder alloy (BGA) is used to establish mid-level interconnects (MLI) between the patch and the interposer. The interposer is an LGA that connects to the board through a socket.
MLI bump pattern has cavities to support air core inductors designed within the patch that function as Integrated Voltage Regulators(?)
2.5D/TSV Interposers: Weighing Pros & Cons
Benefits: 1. High density integration facilitating greater functionality (digital/logic, memory, analog, MEMS, optoelectronics, signal & power management) in smaller footprint. 2. Improved memory bandwidth and power management. 3. Faster signal speeds & lower parasitics (noise, crosstalk, latencies, propagation delays, interference) 4. Modular design & die-partitioning permits use of mixed IC technology, improving product development & supply-chain flexibility/scalability. 5. Best of both worlds between PoP(= modularity, shorter & less complex development cycles/TTM)& SoC (= increased wiring densities, faster signal speeds, memory/power benefits) type package architectures. Issues & concerns: 1. Cost: KGD yield related issues, manufacturing & test complexities drive cost upwards. 2. Thermal management. While 3D stacked memory (NAND Flash on S/D/RAM) and memory-on-logic(DSP with DRAM, GPU with SRAM) configurations have been successfully demonstrated & mass-produced, logic on logic has largely been beyond reach of thermal envelopes of existing packaging materials. 3. Manufacturing complexities: Additional processes such as backgrinding, bonding/debonding to carrier wafers & stacking are involved. Considerations include deciding between via-first, via-middle, via-last flows; F2F, F2B chip-attach schemes; W2W, D2D, D2W integration configurations. Thin die handling/die-attach and capillary underfill flow in tight interstitial spaces are challenges. PAM/NCP/NCF's with TCB will be needed. 4. Supply chain / ownership/ business model needs clarity: backgrinding/stacking/bumping/dicing/bonding/debonding operations need clear process owners. Who does what & what if things go wrong-these questions need clear answers. 5. Design tool kit to address multiple aspects (substrate/SoC design, SI/PI, RF & power management, EDA) is still in the exploratory & pathfinding phase. 6. Lack of standards across the industry for 2.5D/3D TSV facilitation. These are expected to be developed as needed and customized as required.
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Packaging interconnects have over time evolved from leadframes/terminations through wirebond/die-attach to flip-chip attach (for higher performance applications) & wafer-level packaging / WLP (for cost sensitive products). Slowdown in transistor scaling and the continuing need for higher performance & miniaturization at lower costs has led to adoption of advanced packaging technologies. While interposer based package integration (3D TSV/2.5D) has slowly but surely been adopted for SoC type high end devices / performance driven applications (such as servers/datacenters), Fanout has been gaining popularity at the other end of the spectrum for low-to-mid cost applications (such as mobile, automotive & consumer). Fanout approaches primarily include WLFO / FOWLP but also higher density (HDFO) SiP type enablements such as FOCoS and FOPoP.
FOWLP is an extension of WLP using a redistribution layer (RDL) that allows high density integration at low cost, and is quickly becoming the new packaging technology of choice across a wide range of mobile and/or consumer applications. Traditionally, FO has been face-down & chip-first, but newer fanout methodologies include chip-last (SWIFT) and face-up (DECA/M-Series) techniques. InFO or Integrated Fanout is an implemententation of FOWLP, developed by TSMC used in the application processors of Apple's latest flagship iPhones.
FOWLP & alternatives
Performance & functionality drive high I/O, fine pitch, high density interconnect requirements that require advanced package integration technologies. 3D/2.5D TSV based technologies enable such package integration, but these are burdened with high cost and process complexities. The other approach is "fan-out" or FO-WLP.
Some of the implementations of FO-WLP are eWLB (Infineon), RCP (Freescale), SWIFT (Amkor) & InFo (TSMC).
Traditionally, FO-WLP have used "chip-first" approaches, where chip is processed before RDL. Process includes wafer dicing, reconstitution, molding, RDL/bump formation & singulation. Otherwise, a "chip-last" technique may also be used where chip is processed after RDL. Here, the process steps involve first creating the RDL on a carrier wafer, chip-attaching the top-die (CoW), molding & singulation. In either case, generating the RDL requires expensive fab/foundry (BEOL) class equipment that may not be readiy available at the OSAT - so this adds to assembly cost.
A fan-out alternative that allows the OSAT's to leverage existing flip-chip assembly technology & infrastructure is FO chip-last package (FOCLP) that entails dicing, flip-chip assembly on 1L/coreless/ETS substrate in strip form, followed by molding & singulation. This does not require fab-class equipment for RDL processing, and therefore can keep costs low.
Inputs below from:
https://semiengineering.com/fan-out-wars-begin/
https://www.3dincites.com/2016/08/fan-out-packaging-the-most-dynamic-advanced-packaging-platform-will-it-be-sustainable-long-term/
http://electroiq.com/insights-from-leading-edge/2015/03/iftle-233-package-shrinkage-continues-with-ase-foclp/
http://electroiq.com/insights-from-leading-edge/
http://www.nepes.co.kr/web/nepes_eng/semi_SiP
Comparison across TSV, SLIM, SWIFT & Conventional WLFO/FOWLP/WLCSP
FO-WLP -> InFO PoP (TSMC) and SWIFT (Amkor)
Traditional FO-WLP (or WLFO) use "chip-first"
approaches. This needs committing expensive KGD before the wafer
reconstitution/reconfiguration process and is therefore at risk of yield loss
from the RDL build up process. Also, capabilities of photoresist/dielectric
processing with steppers/masks are challenged by the planarity of the
wafer-level molding process, resulting in limitations in the design rules for
these packages, with the tightest L&S being in the range of 6-10um.
Typically only 1 or 2 RDL layers can be supported. Additionally, 3D POP package
formats have new complexities, since those entail complex laser drilling/Cu
plating for the TMV's/Cu Pillars on back side of the molded wafers to establish
the 3D interconnects to the front side RDL.
In contrast, SWIFT uses a "chip-last" approach,
since the RDL/backside is first separately built up on a carrier wafer, and
then the KGD is chip-attached using a CoW approach. Since RDL buildup is now
done pre-molding, the dielectric topology/planarity allows much finer L&S
with stepper/mask capabilities, allowing upto 2/2 L&S and upto 3 RDL
layers. This technology is also compatible with large die / package body sizes,
supports upto 30um die pitch (Cu ubumps) and allows for 3D PoP integration
through TMV's or Cu posts/pillars.
SLIM/SWIFT are package integration technologies developed by
Amkor to bridge the L/S routing capability gap between applications needing TSV
(5um), primarily targeted for WLP - but also extended to flip-chip packages,
leveraging conventional techniques & capabilities, allowing for high
density & smaller footprints at relatively low cost.
InFO: A New Approach
Traditionally, high end smartphone chips have used PoP approach, where a wirebonded memory/LPDDR (DRAM) package is stacked on top of an AP that uses flip-chips interconnecting the SoC with a laminate substrate. InFO is a new packaging approach and an alternative to this traditional technique, disrupting the status quo, with numerous benefits in terms of improved performance & thinner package form factors.
InFO combines POP with FO-WLP packaging technologies, and stacks the wirebonded memory package on a FO-WLP SoC, that no longer requires flip-chip interconnects & the laminate substrate. This reduces the thickness of the package and improves performance by reducing the vertical path for signal propagation and allowing finer L&S routing capabilities by using an RDL instead of a laminate substrate. This in turn, improves SI/PI parasitics (crosstalk, impedance, transmission loss, PDN noise, jitter & leakage), improves DRAM/memory bandwidth and reduces power consumption. Package thermals on an InFO POP is expected to be superior to the conventional FCPOP's, with InFO generating lower Tjmax & Rja (for both logic SoC & DRAM) and being able to support larger TDP's for the same Tj. In addition, InFO provides high flexibility/capability for homogenous or heteregenous multi-chip package integration between active and/or passive devices, either at 2D using RDL or 3D with TIV (Through InFO Vias).
Advanced Package Integration Implementation
Infineon: eWLB, Freescale: RCP (Redistributed Chip Package) -> First examples of WLFO implementation
STMicroelectronics uses 3D-eWLB
ASE has FOPOP technology
Amkor POSSUM is implementation of Altera's ASIC + FPGA integration
Apple A8/A9 processor is 3D-POP using conventional FC/WB techniques integrating AP and Elpida memory (DDR3/4)
Samsung has DDR4 DRAM modules that stacks multiple chips with 3D TSV integration
Micron has HMC DRAM memory stack that integrates 3D DRAM/DDR memory stack with logic controller with TSV providing high bandwidth memory, implemented in Altera STRATIX and Intel Knight's Landing platforms
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