Package Design / Product Development

Package Design Flow

Functional requirements & performance specifications scoped > Architectural Design (SCHEMATIC CAPTURE) > Functional Design (RTL) > Logic Design (GATE level) > Circuit Design (TRANSISTOR level) > Physical Design (LAYOUT, ROUTING, SI/PDN Analysis & VERIFICATION)

Physical design comprises of partitioning, floorplanning, placement, clock tree synthesis, routing, SI/PDN analysis & DFM.

SI/PDN analysis is an important part of Physical Design. Pre-layout, the focus is on downselecting interconnect technologies, substrate/board stackups, defining component specifications & material sets, pin-assignments, net topologies, establishing design rules/constraints. Post layout, the emphasis shifts to verification of SI, noise & parasitic characterization (including reflection, cross-talk, ground-bounce), timing analysis (understanding latencies , propagation delays, rise times bandwidths & bottlenecks).


Package Design Tools for DFM & Verification

Zuken/QPV: Signal integrity
Valor: DFM DRC
Caliber: Connectivity checks
IPX: Bump rule DRC


Design verification is done pre-silicon tapeout, validation is run post first Silicon.

Verification involves software simulation using RTL, HDL(Verilog & VHDL) & hardware emulation including FPGA prototyping.

Lab tools for SI/PDN verification & validation:
Logic Analyzer, digitizing oscilloscopes, spectrum analyzer, time domain reflectometry, signal generator, sequence controller






Package Design File Types

Cadence APD: generates .mcm formats
Cadence SIP : generates .sip formats

.sip files can be used to extract.gds/.sf files for silicon or gerber files for substrate.

SIP provides greater flexibility/functionality over APD, such in terms of netlist management, DRC's, 3D visualization, etc.



DFT / Structural Test Coverage


 ATPG: Digital logic [flip-flop, NAND/NOR]

MBIST: memories, cache & ROM

BSDL: JTAG implementation of I/O Boundary Scan





Product Development: Womb to Tomb, Cradle to the Grave

Technology Qual -> Node developed & validated -> Product Enablement -> Development Kickoff -> Logic Design -> Physical Design (partitioning/floorplanning/placement & layout) -> DRC -> Review/approve substrate drawings for substrate manufacturing & assembly bringup (tooling: jigs, fixtures, stencils, sockets, etc) -> Tapeout -> FAI -> First Silicon -> Assembly process development, optimization & validation (manufacturing windows & corner studies,material screens, material/equipment/process/recipe readiness) -> EVT builds -> Test charz (defects & yield, pareto of rejects) -> Reliability Charz (AM qual, margin assessment, robustness testing, component & board level testing) -> customer prototype builds -> Qualification -> Production Readiness (process/material specs, bill-of-materials, product flows, vendor lists, capacity & resource planning) -> Production Release through soft ramp -> HVM -> QMP(SPC/CoC) -> EOL