FO-WLP -> InFO PoP (TSMC) and SWIFT (Amkor)
Traditional FO-WLP (or WLFO) use "chip-first" approaches. This needs committing expensive KGD before the wafer reconstitution/reconfiguration process and is therefore at risk of yield loss from the RDL build up process. Also, capabilities of photoresist/dielectric processing with steppers/masks are challenged by the planarity of the wafer-level molding process, resulting in limitations in the design rules for these packages, with the tightest L&S being in the range of 6-10um. Typically only 1 or 2 RDL layers can be supported. Additionally, 3D POP package formats have new complexities, since those entail complex laser drilling/Cu plating for the TMV's/Cu Pillars on back side of the molded wafers to establish the 3D interconnects to the front side RDL.
In contrast, SWIFT uses a "chip-last" approach, since the RDL/backside is first separately built up on a carrier wafer, and then the KGD is chip-attached using a CoW approach. Since RDL buildup is now done pre-molding, the dielectric topology/planarity allows much finer L&S with stepper/mask capabilities, allowing upto 2/2 L&S and upto 3 RDL layers. This technology is also compatible with large die / package body sizes, supports upto 30um die pitch (Cu ubumps) and allows for 3D PoP integration through TMV's or Cu posts/pillars.
SLIM/SWIFT are package integration technologies developed by Amkor to bridge the L/S routing capability gap between applications needing TSV (<2um L&S) v/s standard packaging (>5um), primarily targeted for WLP - but also extended to flip-chip packages, leveraging conventional techniques & capabilities, allowing for high density & smaller footprints at relatively low cost. SLIM uses TSV-free interposer wafers (but retains BEoL & RDL, allowing <2um L&S routing) that simplifies interposer MEOL process (by eliminating need for CVD/CMP for TSV reveal during interposer MEOL), thins package form factor and reduces cost & simplifies supply chain (by allowing use of TSV-free wafers). SWIFT, on the other hand, uses passive carrier / interposer wafers that do not contain TSV or BEOL (but retains RDL, allowing 2-5um L&S). Top die could be attached on using CoW approach for both SLIM/SWIFT followed by wafer molding, interposer MEOL and topside RDL routing for POP as needed.
