Mold Embedded Packages (MEP)

Molded Embedded Packages seek to overcome warpage concerns and limitations in z-height that conventional PoP type packages suffer from, where hybrid wirebonded/stacked die memories are stacked on FCBGA logic/ASIC SoC's, as commonly found in AP's of high-end flagship smartphones.

For MEP, first the active logic device is flip-chip attached on a base substrate. Then Cu Core balls are used to mount the top substrate on the base substrate with the interstitial space between the 2 substrates being encapsulated by a molding resin. Finally, BGA solder balls are mounted on the bottom substrate.

Since MEP does not require any gap between top and bottom packages as required in a conventional PoP (BD or MLP-ED/OM), by nature of the package construction, it allows for thinner PoP form factors. Landing pads routed to the top-side of the MEP allow DDR/DRAM memory to be mounted in a PoP format without any limitations from the layout of the (embedded) logic die (unlike conventional PoP's), enabling wide I/O memory interconnect with high bandwidth. This also allows using thinner memories reducing package z-height. Further, MEP packages have good warpage characteristics owing to similar material /structures between top & bottom substrates.