FO-WLP: Chip-First v/s Chip-Last

Performance & functionality drive high I/O, fine pitch, high density interconnect requirements that require advanced package integration technologies. 3D/2.5D TSV based technologies enable such package integration, but these are burdened with high cost and process complexities. The other approach is "fan-out" or FO-WLP.

Some of the implementations of FO-WLP are eWLB (Infineon), RCP (Freescale), SWIFT (Amkor) & InFo (TSMC).

Traditionally, FO-WLP have used "chip-first" approaches, where chip is processed before RDL. Process includes wafer dicing, reconstitution, molding, RDL/bump formation & singulation. Otherwise, a "chip-last" technique may also be used where chip is processed after RDL. Here, the process steps involve first creating the RDL on a carrier wafer, chip-attaching the top-die (CoW), molding & singulation. In either case, generating the RDL requires expensive fab/foundry (BEOL) class equipment that may not be readiy available at the OSAT - so this adds to assembly cost.

A fan-out alternative that allows the OSAT's to leverage existing flip-chip assembly technology & infrastructure is FO chip-last package (FOCLP) that entails dicing, flip-chip assembly on 1L/coreless/ETS substrate in strip form, followed by molding & singulation. This does not require fab-class equipment for RDL processing, and therefore can keep costs low.