InFO combines POP with FO-WLP packaging technologies, and stacks the wirebonded memory package on a FO-WLP SoC, that no longer requires flip-chip interconnects & the laminate substrate. This reduces the thickness of the package and improves performance by reducing the vertical path for signal propagation and allowing finer L&S routing capabilities by using an RDL instead of a laminate substrate. This in turn, improves SI/PI parasitics (crosstalk, impedance, transmission loss, PDN noise, jitter & leakage), improves DRAM/memory bandwidth and reduces power consumption. Package thermals on an InFO POP is expected to be superior to the conventional FCPOP's, with InFO generating lower Tjmax & Rja (for both logic SoC & DRAM) and being able to support larger TDP's for the same Tj. In addition, InFO provides high flexibility/capability for homogenous or heteregenous multi-chip package integration between active and/or passive devices, either at 2D using RDL or 3D with TIV (Through InFO Vias).
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Saturday, October 1, 2016
InFO - A new approach
InFO combines POP with FO-WLP packaging technologies, and stacks the wirebonded memory package on a FO-WLP SoC, that no longer requires flip-chip interconnects & the laminate substrate. This reduces the thickness of the package and improves performance by reducing the vertical path for signal propagation and allowing finer L&S routing capabilities by using an RDL instead of a laminate substrate. This in turn, improves SI/PI parasitics (crosstalk, impedance, transmission loss, PDN noise, jitter & leakage), improves DRAM/memory bandwidth and reduces power consumption. Package thermals on an InFO POP is expected to be superior to the conventional FCPOP's, with InFO generating lower Tjmax & Rja (for both logic SoC & DRAM) and being able to support larger TDP's for the same Tj. In addition, InFO provides high flexibility/capability for homogenous or heteregenous multi-chip package integration between active and/or passive devices, either at 2D using RDL or 3D with TIV (Through InFO Vias).
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