System in Package

SiP = ASIC SoC (CMOS Logic) + HBM (DRAM stack) on
-2.5D Si interposer w/ TSV (CoS or CoW assembly flow) (L&S: <2um, highest cost)
-2.5D Si interposer w/o TSV (or SLIM) (CoS or CoW assembly flow) (L&S: <2um, medium cost)
-2.1D organic interposer or POI or iTHOP (L&S: 2-10 um, medium to possibly lower cost)

Packaging Technology

1st level interconnects: FC or WB

Flip Chip Attach:
MR (SnAg or CuP w/ SOP or CuBOL w/o SOP) w/CUF or MUF
TCFC (TCNCP or TCNCF or TCCUF)

Substrate:
Singulated or strip
ETS or SAP

Package:
BGA, LGA, CSP, POP, QFN, WLP, SiP

System Cooling v/s TDP

System Cooling = Rca & Tambient

As system cooling improves (reducing Rca & Tambient), solution can support larger TDP's.

For any given system cooling, Indium can support larger TDP compared to Poly TIM
For any given TDP, more system cooling (or lower Rca / lower Tamb) is needed for poly TIM solution v/s Indium TIM.

As power increases, case temperature has to be progressively lowered through system cooling, to maintain the same junction temperature. When the power increases, and the case temperature is not controlled (effectively by the system cooling), then junction temperature will rise.

When junction temperature exceeds a certain pre-set threshold (usually Tjmax), DVFS will trigger, reducing voltage and frequency, in turn reducing power (and computing performance), and thereby bringing the junction temperature down.

Datacenter Anatomy

CPU +components => NODES => BLADES/SLEDS + CHASSIS => RACKS => CLUSTERS

Hypothesis Testing in JMP

One sample t-test
Used to compare mean of 1 population/sample to a hypothesized value
Null hypothesis states that population/sample mean is equal to hypothesized value
[Analyze-> Distribution, select TEST MEAN]


Two sample t-test
Used to compare means of 2 populations/samples with each other. Continuous variable (Y) v/s 2-level single categorical variable/factor (X)
Null hypothesis states that means of the 2 populations/samples are equal to each other
[Analyze -> Fit Y by X, select MEANS/ANOVA/POOLED-T or T-TEST]


One Way Anova
Used to compare means of 3 or more populations/samples. Continuous variable (Y) v/s single categorical variable with 3 or more levels (X)
Null hypothesis states that means of all populations/samples/levels are equal to each other.
[Analyze -> Fit Y by X, select MEANS/ANOVA + COMPARE MEANS]


Two Way (Factorial) ANOVA
Used to study effects of 2 categorical variables/factors and their interaction on single response. Continuous variable (Y) v/s two categorical variables (X1, X2)
Null hypothesis states that factors do not have a significant effect
[Analyze -> Fit Model, select LS MEANS PLOT]

JMP Data Types & Graphs

Variables are either Continuous or Categorical (Nominal or Ordinal).
Continuous (Y) v/s Continuous (X) --> BIVARIATE
Continuous (Y) v/s Categorical (X) --> ONE WAY ANOVA

Categorical(Y) v/s Categorical (X) --> CONTINGENCY
Categorical (Y) v/s Continuous (X) --> LOGISTIC

HPC & CoProcessors

Traditionally, HPC environment -> Co Processors or Accelerators (non bootable) combined with server x86 processors, to offload tasks, interfacing through PCIe, typically GPU class SoC's since these provide high bandwidth performance. GPU SoC need GDDR5, server processors will need their own memory (DDR4),this increases system complexity and power consumption. Although this approach is good for certain applications, in other cases, especially with a large mix of single-threaded, serial & serial/parallel mixed applications, this has severe limitations. NVidia Tesla (K40) & Intel Knights Corner are examples of this implementation. Intel's Knights Landing is a paradigm shift in HPC, since it eliminates the need for a coprocessor. This is a fully bootable x86 server/accelerator fused with high capacity DDR4 controllers as a single SoC packaged as an MCM with 8 stacks of HMC (multi channel DRAM with upto 16GB memory). This reduces system complexity and improves system efficiency.