Smartphone Components

Antenna + Switch & RFFE, Filter, Duplexer, Amplifier, Transceiver, Baseband, Application Processor [SOC + LPDDR3], Memory [Flash / SSD], PMIC, Battery, Audio CODEC, Wifi/BT/GPS/NFC, Gyroscope/Accelerometer/Sensors, Touch controller, Microcontroller, Screen

Package Design File Types

Cadence APD: generates .mcm formats
Cadence SIP : generates .sip formats

.sip files can be used to extract.gds/.sf files for silicon or gerber files for substrate.

SIP provides greater flexibility/functionality over APD, such in terms of netlist management, DRC's, 3D visualization, etc.

Chip Types

MPU, MCU, DSP, AP & ASIC's such as FPGA's. & PLD's

Memories: ROM / cache, DRAM/SRAM (DIMM), HDD, SSD (Flash NAND/NOR)

Apple SoC in IPhones

A10 used InFO for the first time in iPhone 7.

A11 -> iPhone 8, A10 -> iPhone 7
A9  -> iPhone 6s, A8 ->  iPhone 6
A7  -> iPhone 5s, A6  -> iPhone 5

Advanced Silicon/Package Integration Schemes at Intel

EMIB: Embedded Multi Interconnect Bridge

Localized high density package routing with ability to interconnect multiple die in an organic substrate without requiring TSV. Allows integration of multiple large die without being limited by reticle size of the interposer. Driven by  the needs of high bandwidth CPU-DRAM (HBM) integration with low power consumption, and particularly attractive for large die. Leverages existing assembly processes and organic substrate technology. Lower cost than competing technologies of TSV & SLIM based package integration.


Thin silicon bridges are first fabricated using standard BEOL interconnects.  An organic laminate substrate is also manufactured using standard processes upto the final build up layers. Here an additional process step is required wherein a cavity is created and the silicon bridge is inserted / and held in place with an adhesive before completing the final build up and localized fine microvia formation around the bridge region. During subsequent assembly, chip-attached is completed through a TCB/TCCUF process.


PoINT: Patch on Interposer

Implemented on Intel Skylake CPU, this uses a high density / thin core substrate (PATCH) stacked on lower density/ standard / lower cost organic laminate (INTERPOSER). Assembly involves first attaching SoC die to patch, and then attaching die+patch module to interposer. Due to concerns related to warpage of die+patch module, a low temp solder alloy (BGA) is used to establish mid-level interconnects (MLI) between the patch and the interposer. The interposer is an LGA that connects to the board through a socket.

MLI bump pattern has cavities to support air core inductors designed within the patch that function as Integrated Voltage Regulators(?)

DFT / Structural Test Coverage

 ATPG: Digital logic [flip-flop, NAND/NOR]

MBIST: memories, cache & ROM

BSDL: JTAG implementation of I/O Boundary Scan

Server uP tech specs

Clock speed, L3 cache, DDR/PCI gen, # of cores, TDP, Tjmax, Technology Node

Product Qualification

BI/HTOL/LU/ESD(HBM/CDM)/THB or BHAST/PCT

Server Processor IP / Macro Blocks

DDR, PCIE, L3 cache, SATA, USB, GPIO, PLL, SGMII, SERDES, APC/CBF, SRAM, UCI, PHY

SI / PI

PDN. Crosstalk. Parasitics. Latency. Bandwidth. EMI/EMC. RC delay. Resistance, Capacitance, Inductance, Impedance.

Droop, insertion loss, return loss, impedance matching, jitter, rise time, transmission line effects, eye diagram (eye ht ->mv, eye width->ps), leakage, transmission loss

Conflict Resolution

Turtle : Avoid
Bear: Accommodate
Shark: Compete
Fox: Compromise
Owl: Collaborate

Myers-Briggs Personality Test

Covey's Time Management Matrix

High Importance, High Urgency: PREVENT

Low Importance, Low Urgency: AVOID

High Importance, Low Urgency: PLAN

Low Importance, High Urgency: MANAGE

Project Management Fundamentals

Needs: RFI/RFP/SOW
Solution/Plan Definition: Charter (Goals, Objectives, Team, Stakeholders, Sponsors, Deliverables, Decisions, Risks, Assumptions) & WBS (defines Scope, Schedule/Time, Budget), Resources (allocation/assignment/leveling/balancing), Duration estimates/Dependencies (FS, SS, FF, SF), AON/Critical Path, Gantt Chart
Execute / Perform: Manage, track (variance to baselines, progress status, corrective action), control (PERT/CPM/EVMS), report, review.
Close-out. Document. Lessons Learned.

EVMS

Earned Value Management System is a quantitative methodology to track and control project progress by expressing project status in $ metrics.

Planned Value (PV) = Budgeted cost of work planned/scheduled
Earned Value (EV) = Budgeted cost of work performed
Actual Cost (AC) = Actual expenses of work performed

EV/PV = Schedule Index. EV - PV = Schedule Variance
<1 SI or (-) SV indicates schedule delays.

EV/AC = Cost Index. EV - AC = Cost Variance
<1 CI or (-) CV indicates cost over-runs.

Project Management

Triple constraint, iron triangle: Scope, schedule, budget => Quality & Performance
Plan the work, work the plan
If you dont know where you are going, you wont end up where you are going
Failing to prepare is preparing to fail
Plans are useless, but planning is indispensable - Eisenhower
Luck is where opportunity meets preparation
Pickle jar: task prioritization
Task dependencies, conditionalities, contingencies
Resource leveling & load balancing
Resource allocation & reassignment
Change control, risk management
PERT / EVMS
Waterfall v/s Agile / SCRUM project methodology
PERT / CPM

DVFS in Multi Core Processors

Improved performance in modern-day microprocessors has been achieved through a combination of higher processor frequency / clock speeds, use of shrinking / advanced technology nodes & a generally increasing number of CPU cores in the SoC. Increasing core count translates to smaller physical size of the individual cores and a tightly packed core distribution/layout on the chip.

Smaller cores imply higher power density per core, which increases thermal resistance (Rja) of the packaging solution. Higher Rja at the same total power dissipation (P), increases the junction temperature (Tj). When Tj approaches a set/predefined threshold (commonly Tjmax), in modern day processors, DVFS (Dynamic Voltage Frequency Scaling) will trigger that reduces operating voltage and clock speed/frequency, which in turn, can directly impact computing performance. With reduced voltage & frequency, total power (P) and power density per core will both be lowered. When total power & core power density both scale downward by the same extent, since Rja (being defined by material & geometry parameters) remains relatively constant, this results in lowering of Tj. In this way, by means of DVFS, a correlation may be established between change in total power (P) and the impact on computing performance of the chip.

When cores are tightly packed around one another in the SoC floorplan, that can also adversely affect package thermals and Rja. It may be shown through simulation & analysis, that if power density per core is reasonably low and cores may be sufficiently spaced apart from each other in their distribution/layout on the SoC, the die power map may start approaching an idealistic uniform power density solution. This demonstrates that core distribution/layout and core spacing are an important items for consideration towards power map optimization during die floorplanning in early product design.

Fails - Exact or Censored

Failure times are either EXACT or CENSORED

Right censored or suspended = Unit has survived when test is stopped

Interval censored = Unit has failed between "Last Inspection" and now

Left censored = Similar to Interval Censoring but "Last Inspection"/Start is 0

Extrapolating Accelerated Test TTF to Predict Use Level Lifetime

Collect TTF at multiple accelerated stress levels.
Fit TTF data to life-distribution (for eg. 2P Weibull) for each stress level, and estimate parameters - each distribution with different eta but same beta (for the same failure mechanism).

Life distribution characteristic (eta) is a function of stress & is equated to stress level using a given Life-Stress-Relationship (LSR) - for eg Eyering Model
Estimate model constants

Now, knowing model constants, estimate eta at various stress levels, including at use level. And knowing beta (for the given failure mechanism) use-level life distribution can be predicted.

FIT Rates

h(t) = hazard rate = f(t)/R(t)
Hazard rate is instantaneous failure rate. But usually, average failure rate for a given time period is more useful, for eg. failure rate per hour.

FIT rate is defined as ppm failure per 1000 hours or number of fails per 10^9 device hours.

Multiply hourly fail-rate by 10^9 to generate FIT rate.

Hourly fail rate = No of rejects / (No of devices x No of hours x AF)

FIT rate = Hourly fail rate x 10^9

No of rejects is determined by Chi-square distribution = [(x^2)/2], commonly at 60% confidence (alpha) and dof: 2r + 2