Chip Types

MPU, MCU, DSP, AP & ASIC's such as FPGA's. & PLD's

Memories: ROM / cache, DRAM/SRAM (DIMM), HDD, SSD (Flash NAND/NOR)

Apple SoC in IPhones

A10 used InFO for the first time in iPhone 7.

A11 -> iPhone 8, A10 -> iPhone 7
A9  -> iPhone 6s, A8 ->  iPhone 6
A7  -> iPhone 5s, A6  -> iPhone 5

Advanced Silicon/Package Integration Schemes at Intel

EMIB: Embedded Multi Interconnect Bridge

Localized high density package routing with ability to interconnect multiple die in an organic substrate without requiring TSV. Allows integration of multiple large die without being limited by reticle size of the interposer. Driven by  the needs of high bandwidth CPU-DRAM (HBM) integration with low power consumption, and particularly attractive for large die. Leverages existing assembly processes and organic substrate technology. Lower cost than competing technologies of TSV & SLIM based package integration.


Thin silicon bridges are first fabricated using standard BEOL interconnects.  An organic laminate substrate is also manufactured using standard processes upto the final build up layers. Here an additional process step is required wherein a cavity is created and the silicon bridge is inserted / and held in place with an adhesive before completing the final build up and localized fine microvia formation around the bridge region. During subsequent assembly, chip-attached is completed through a TCB/TCCUF process.


PoINT: Patch on Interposer

Implemented on Intel Skylake CPU, this uses a high density / thin core substrate (PATCH) stacked on lower density/ standard / lower cost organic laminate (INTERPOSER). Assembly involves first attaching SoC die to patch, and then attaching die+patch module to interposer. Due to concerns related to warpage of die+patch module, a low temp solder alloy (BGA) is used to establish mid-level interconnects (MLI) between the patch and the interposer. The interposer is an LGA that connects to the board through a socket.

MLI bump pattern has cavities to support air core inductors designed within the patch that function as Integrated Voltage Regulators(?)

DFT / Structural Test Coverage

 ATPG: Digital logic [flip-flop, NAND/NOR]

MBIST: memories, cache & ROM

BSDL: JTAG implementation of I/O Boundary Scan

Server uP tech specs

Clock speed, L3 cache, DDR/PCI gen, # of cores, TDP, Tjmax, Technology Node

Product Qualification

BI/HTOL/LU/ESD(HBM/CDM)/THB or BHAST/PCT

Server Processor IP / Macro Blocks

DDR, PCIE, L3 cache, SATA, USB, GPIO, PLL, SGMII, SERDES, APC/CBF, SRAM, UCI, PHY

SI / PI

PDN. Crosstalk. Parasitics. Latency. Bandwidth. EMI/EMC. RC delay. Resistance, Capacitance, Inductance, Impedance.

Droop, insertion loss, return loss, impedance matching, jitter, rise time, transmission line effects, eye diagram (eye ht ->mv, eye width->ps), leakage, transmission loss