2.5D adoption

Image CMOS sensors/DSP, DRAM/flash memory stacks -> early adopters (Sony, SK Hynix, Micron, Samsung, Toshiba)
High performance FPGA integration (Xilinx Vertex series)
High performance graphics (AMD Fiji/Fury)
Servers & networking (Altera, IBM, Huawei, Cisco)

Copper Pillar: why, when & where

Mass reflow w/CUF (CuP) or Thermo compression bond (TCB/TCFC) -> TC-CUF, TC-NCP, TC-NCF
Electrical performance (current carrying capabilities, EM, fine pitch requirements) are driving CuP.
Mass reflow w/ Cu-pillar (CuP) maximizes UPH and therefore minimizes assembly cost. However, for large die packages, MR generates warpage concerns that can result in ELK/CPI issues. To counter this and lower package stresses, TCB or TCFC are process alternatives (but are low UPH options that end up increasing assembly cost/complexity):
TC-CUF: relatively lower cost alternative, but capillary UF flow may need vacuum underfill or pressure curing
TC-NCP: relatively medium cost alternative
TC-NCF: highest cost, application limited to thin die/ smaller FF packages/ ultra fine pitch
Shrinking pitch & die size: MR + Pb-free solder, MR + CuP/CuBOL, TC-CUF, TCNCP, TCNCF

AMD

Opteron 3000: low power (25-65W), low cost, 1S server, Piledriver core
Delhi, Orochi AM3

Opteron 4000: mainstream (35-95W), 1S or 2S, Piledriver core
Seoul, Orochi C32

Opteron 6000: high performance (100-150W), 2S or 4S, Piledriver core
Abu Dhabi, Orochi G34 -> Warsaw refresh

Opteron X: Kyoto, low power (11-22W), microserver (Jaguar core / mobile class)
Opteron A: Seattle, ARM based server(25W), ARMv8 64-bit Cortex A57
Roadmap:
Berlin (Steamroller core) & Toronto (Excavator core)
Next-gen microarchitectures: Zen (14/16nm x86 core) and K12 (ARMv8)

Intel

New u-architecture = TOCK; process node shrink = TICK
Haswell (22nm TOCK), Broadwell (14nm TICK)
Atom (Silvermont 22nm) -mobile SoC based core, optimized for low power, energy-efficient, scaleout applications
Xeon (Haswell 22nm or Broadwell 14nm)-> D (low end/high density server/microservers), E3 (desktop-client class/1S), E5 (mainstream or enhanced performance-EP/2S or 4S), E7 (mission critical or EX-expandibility, 4S+)
Itanium (65nm & 32nm), implementing IA-64 instruction set that is non x86 compatible
uP specs: Clock speed GHz, cache MB, DRAM bandwidth GB/s, TDP W, # cores & threads, bitwidth
SKYLAKE: 14nm TOCK (uarchitechture change), CANONLAKE: 10nm TICK (node shrink)
Denverton (Airmont 14nm) is follow on to Atom (Silvermont 22nm)

Microservers

Low power rack-mount high density modular approach, with each module or "sled" or "cartridge" being a full server, that may either be single or dual socketed
More suited to "scaleout" applications that rely on increasing/deploying more nodes & modules instead of "scaleup" that depend on boosting performance by increasing clock speed or adding more CPU cores. Cloud based solutions rely on distributed applications/computing and therefore tend to be supported by microservers - that improve power efficiency, redundancy, availability & cost management.

GSM, GPRS, EDGE (2.5G) -> TDMA
CDMA, WCDMA, EVDO(3G), HSPA(3.5G)
LTE (3.9G)

ARMv8 64-bit

ARMv8 is new ISA (Instruction Set Architecture) that enables 64-bit computing improving CPU performance, paving the path forward for ARM based SoC's to compete with x86 in servers: Cortex A57 and Cortex A72 are standard ARMv8 cores, but there are several custom ARMv8 cores being developed in the industry

Server 101

Server system technology
Platform = SoC processor + logic chipsets (North Bridge/South Bridge) + DIMM + Baseboard Management Controller + PCB + Graphic Cards

North Bridge = Memory controller + PCIe controller
South Bridge = SATA (HDD & SSD)/USB/Ethernet/MAC/Flash/SPI (serial peripheral interface)/LPC(low pin count)
SoC = CPU [+ GPU] + memory (cache) + memory controller + I/O controller (PCIe, SATA, USB, Gbe) + system bus
Baseboard management controller provides for remote monitoring/management of server boards by system admin
RAID: Redundant Array of Inexpensive Disks -> applied to HDD/SSD -> connect to processor through SATA interface

Server Processor performance attributes: Multicore (parallel processing), multithreading (virtualization), clock speed, cache, memory bandwidth & latency, logic chipset, memory subsystem, system bus, technology node( 14 FinFet v/s 16nm), ISA ( instruction set architecture: x86 v ARM), ECC (error correction code), RAS (reliability, availability & serviceability)

Rack & blade servers Chassis of racks, with each rack supporting: servers, switches, networking & storage, peripherals, adapters & cards, power supplies, fans & cooling equipment
1RU or 1U is 1.75" high, 19" wide
Blade server can fit into 19" rack and may be 4U to 10U (or larger) in height - and can support multiple blades, with each blade being processor + logic chipsets + memory + storage + network +I/O controllers/interfaces

Blade servers also include fabric modules + switch modules + power management modules, sometime in separate cards in rack-mount chassis

Software Windows Server supports x86 only, not ARM
Commercially available Linux platforms:
Ubuntu (Canonical) -> supports x86, ARM
Suse Linux Enterprise Server /SLES (Novell) & Red Hat -> supports x86, not validated for ARM
Linaro: industry consortium to develop open source Linux software for ARM based SoC's