Antenna + Switch & RFFE, Filter, Duplexer, Amplifier, Transceiver, Baseband, Application Processor [SOC + LPDDR3], Memory [Flash / SSD], PMIC, Battery, Audio CODEC, Wifi/BT/GPS/NFC, Gyroscope/Accelerometer/Sensors, Touch controller, Microcontroller, Screen
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Monday, March 26, 2018
Smartphone Components
Antenna + Switch & RFFE, Filter, Duplexer, Amplifier, Transceiver, Baseband, Application Processor [SOC + LPDDR3], Memory [Flash / SSD], PMIC, Battery, Audio CODEC, Wifi/BT/GPS/NFC, Gyroscope/Accelerometer/Sensors, Touch controller, Microcontroller, Screen
Sunday, November 12, 2017
Package Design File Types
Cadence APD: generates .mcm formats
Cadence SIP : generates .sip formats
.sip files can be used to extract.gds/.sf files for silicon or gerber files for substrate.
SIP provides greater flexibility/functionality over APD, such in terms of netlist management, DRC's, 3D visualization, etc.
Cadence SIP : generates .sip formats
.sip files can be used to extract.gds/.sf files for silicon or gerber files for substrate.
SIP provides greater flexibility/functionality over APD, such in terms of netlist management, DRC's, 3D visualization, etc.
Sunday, October 29, 2017
Chip Types
MPU, MCU, DSP, AP & ASIC's such as FPGA's. & PLD's
Memories: ROM / cache, DRAM/SRAM (DIMM), HDD, SSD (Flash NAND/NOR)
Apple SoC in IPhones
A10 used InFO for the first time in iPhone 7.
A11 -> iPhone 8, A10 -> iPhone 7
A9 -> iPhone 6s, A8 -> iPhone 6
A7 -> iPhone 5s, A6 -> iPhone 5
Saturday, October 28, 2017
Advanced Silicon/Package Integration Schemes at Intel
EMIB: Embedded Multi Interconnect Bridge
Localized high density package routing with ability to interconnect multiple die in an organic substrate without requiring TSV. Allows integration of multiple large die without being limited by reticle size of the interposer. Driven by the needs of high bandwidth CPU-DRAM (HBM) integration with low power consumption, and particularly attractive for large die. Leverages existing assembly processes and organic substrate technology. Lower cost than competing technologies of TSV & SLIM based package integration.
Thin silicon bridges are first fabricated using standard BEOL interconnects. An organic laminate substrate is also manufactured using standard processes upto the final build up layers. Here an additional process step is required wherein a cavity is created and the silicon bridge is inserted / and held in place with an adhesive before completing the final build up and localized fine microvia formation around the bridge region. During subsequent assembly, chip-attached is completed through a TCB/TCCUF process.
PoINT: Patch on Interposer
Implemented on Intel Skylake CPU, this uses a high density / thin core substrate (PATCH) stacked on lower density/ standard / lower cost organic laminate (INTERPOSER). Assembly involves first attaching SoC die to patch, and then attaching die+patch module to interposer. Due to concerns related to warpage of die+patch module, a low temp solder alloy (BGA) is used to establish mid-level interconnects (MLI) between the patch and the interposer. The interposer is an LGA that connects to the board through a socket.
MLI bump pattern has cavities to support air core inductors designed within the patch that function as Integrated Voltage Regulators(?)
Localized high density package routing with ability to interconnect multiple die in an organic substrate without requiring TSV. Allows integration of multiple large die without being limited by reticle size of the interposer. Driven by the needs of high bandwidth CPU-DRAM (HBM) integration with low power consumption, and particularly attractive for large die. Leverages existing assembly processes and organic substrate technology. Lower cost than competing technologies of TSV & SLIM based package integration.
Thin silicon bridges are first fabricated using standard BEOL interconnects. An organic laminate substrate is also manufactured using standard processes upto the final build up layers. Here an additional process step is required wherein a cavity is created and the silicon bridge is inserted / and held in place with an adhesive before completing the final build up and localized fine microvia formation around the bridge region. During subsequent assembly, chip-attached is completed through a TCB/TCCUF process.
PoINT: Patch on Interposer
Implemented on Intel Skylake CPU, this uses a high density / thin core substrate (PATCH) stacked on lower density/ standard / lower cost organic laminate (INTERPOSER). Assembly involves first attaching SoC die to patch, and then attaching die+patch module to interposer. Due to concerns related to warpage of die+patch module, a low temp solder alloy (BGA) is used to establish mid-level interconnects (MLI) between the patch and the interposer. The interposer is an LGA that connects to the board through a socket.
MLI bump pattern has cavities to support air core inductors designed within the patch that function as Integrated Voltage Regulators(?)
Sunday, October 22, 2017
DFT / Structural Test Coverage
ATPG: Digital logic [flip-flop, NAND/NOR]
MBIST: memories, cache & ROM
BSDL: JTAG implementation of I/O Boundary Scan
MBIST: memories, cache & ROM
BSDL: JTAG implementation of I/O Boundary Scan
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Smartphone Components
Antenna + Switch & RFFE, Filter, Duplexer, Amplifier, Transceiver, Baseband, Application Processor [SOC + LPDDR3], Memory [Flash / SSD...
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Molded Embedded Packages seek to overcome warpage concerns and limitations in z-height that conventional PoP type packages suffer from, w...
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L-Gate: Technology/Product Development L-1: Explore / PC1 L 0: Define / PC2 & T/O L 1: Enable/BKM determination L 2: Implement/BK...
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Backside processing done at the OSAT on TSV wafers that involves TSV reveal & RDL/C4 interconnect processing, used in 2.5D/3D TSV pac...