TCNCP with OSP based surface finish

TCNCP requires OSP surface finish (low cost, fine pitch process margins v/s Sn based finishes, controlled solder wetting v/s EPIG finish). However this requires use of fluxing agents in NCP material, to remove oxides during thermal compression bonding. Also it is critical to remove any residual OSP from the pad, since the OSP can combine with by-products of the fluxing reaction and lead to NCP entrapment. This therefore, requires an OSP pre-clean step, which comprises of plasma-treatment & chemical deflux, ahead of TCB.

Power cycling

Motherboard, mux board & fan controller board - design & fabrication, DAQ system, Labview software, package + socket + heat sink + wind tunnel/flow channel, system integration, system setup & debug, calibration & testing.

PoP Evolution

PoP is popular package configuration for smartphones, since this format allows integration of AP/baseband logic with DDR(DRAM) in limited space constraints (footprint & height) while maximizing performance (high speed & bandwidth for memory). Over time, has evolved from WB-POP to FC-POP, and now from BD-PoP to MLP-PoP.

Increasing performance requirements drives larger logic die and package body size, thin core or coreless/ETS substrates, all of which increase warpage that make meeting tightening coplanarity requirements, very challenging. Package height constraints further necessitate thin die/substrates that increase coplanarity/warpage concerns.

In addition, higher memory performance drives need for fine pitch memory, that require smaller ball sizes, which translates to smaller collapsed height or clearance between top & bottom packages.

MLP-PoP is an approach that (1) alleaviates above concerns of warpage & coplanarity, by making use of an overmold that adds structural robustness to the package and (2) enables fine pitch memory by improving the clearance between the 2 packages, without needing excessive die thinning.

This may be MLP-ED (exposed die) or MLP-OM (overmold). ED reduces overall package thickness but slightly higher cop/warpage is the resulting tradeoff. Further, this may be MLP-CUF v/s MLP-MUF

However, MLP-PoP requires additional molding processes - and comes at a premium (cost). Lower cost alternative is to use BD PoP with CuBOL for the bottom package, that increases package to package clearance by reducing die-to-substrate standoff.

Apple A Series SoC

L-Gate methodology

L-Gate: Technology/Product Development
L-1: Explore / PC1
L 0: Define / PC2 & T/O
L 1: Enable/BKM determination
L 2: Implement/BKM optimization & corner
L 3: Qualify/BKM validate
L 4: Ramp/PRU
L 5: Production/HVM

TSV process

Front side:
Etch/Dielectric liner/barrier/seed/fill/RDL/passivation/landing pad

Back side:
Temp bond/backgrind & TSV reveal/MEOL/passivation/bump & debond

2.5D flows: CoW v/s CoS

2 primary flows: CoS and CoW (or CoC)
CoW/CoC may be chip-first (attach before interposer MEOL) or chip-last (after interposer MEOL)
Chip-first requires committing expensive die on interposer, without knowing interposer yield, but allows chip-attach on full thickness wafers. [Concern: Assemblly yield]
Chip-last uses KGD & finished interposer (or KGI) and therefore promises higher assembly yield, but requires thin interposer wafer handling (WSS) and therefore increases assembly cost. [Concern: Assembly cost]
CoS leverages existing flip-chip assembly infrastructure and allows test insertion before committing expensive BOM (logic/ASIC/memory die), but large interposer attach to substrate first, generates warpage concerns that may challenge ASIC/logic/memory die attach to interposer. [Concern: Assembly yield for large die]